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8 x7r dielectric general specifications x7r formulations are called ?emperature stable?ceramics and fall into eia class ii materials. x7r is the most popular of these intermediate dielectric constant materials. its tem- perature variation of capacitance is within ?5% from -55? to +125?. this capacitance change is non-linear. capacitance for x7r varies under the influence of electrical operating conditions such as voltage and frequency. x7r dielectric chip usage covers the broad spectrum of industrial applications where known changes in capaci- tance due to applied voltages are acceptable. capacitance range 100 pf to 2.2 ? (1.0 ?.2 vrms, 1khz) capacitance tolerances preferred ?0%, ?0% others available: ?%, +80 ?0% operating temperature range -55? to +125? temperature characteristic ?5% (0 vdc) voltage ratings 10, 16, 25, 50, 100 vdc (+125?) dissipation factor for 50 volts and 100 volts: 2.5% max. for 25 volts: 3.0% max. for 16 volts: 3.5% max. for 10 volts: 5% max. insulation resistance (+25?, rvdc) 100,000 megohms min. or 1000 m - ? min., whichever is less insulation resistance (+125?, rvdc) 10,000 megohms min. or 100 m - ? min., whichever is less dielectric strength 250% of rated voltage for 5 seconds at 50 mamp max. current test voltage 1.0 0.2 vrms test frequency 1 khz performance characteristics 0805 size (l" x w") 5 voltage 10v = z 16v = y 25v = 3 50v = 5 100v = 1 c dielectric x7r = c 103 capacitance code m capacitance tolerance preferred m = 20% k = ?0% a failure rate a = not applicable t terminations t = plated ni and solder 2 packaging 2 = 7" reel 4 = 13" reel a special code a = std. product part number (see page 3 for complete part number explanation)
9 x7r dielectric typical characteristic curves** % d capacitance +12 0 -6 -75 -50 -25 0 +25 +50 +75 +100 +125 temperature c temperature coefficient +6 -12 -18 -24 % d capacitance +10 +20 0 -10 -20 1khz 10 khz 100 khz 1 mhz 10 mhz fre q uenc y d capacitance vs. frequency insulation resistance (ohm-farads) 1,000 10,000 100 0 +20 +25 +40 +60 +80 temperature c insulation resistance vs temperature +100 impedance, v 10 100 1000 frequency, mhz variation of impedance with cap value impedance vs. frequency 1,000 pf vs. 10,000 pf - x7r 0805 0.10 0.01 1.00 1,000 pf 10,000 pf 10.00 impedance, v 110 100 1,000 frequency, mhz variation of impedance with chip size impedance vs. frequency 100,000 pf - x7r 0.1 .01 1.0 1206 0805 10 1210 impedance, v 110 100 1,000 frequency, mhz variation of impedance with chip size impedance vs. frequency 10,000 pf - x7r 0.1 .01 1.0 1206 0805 10 1210 summary of capacitance ranges vs. chip size * standard sizes ** for additional information on performance changes with operating conditions consult avx? software spicap. style 10v 16v 25v 50v 100v 0402* 100pf - 47nf 100pf - 6.8nf 100pf - 3.9nf 0504 100pf - .01? 100pf - 3.3nf 0603* 100pf - 0.22? 100pf - 0.1? 100pf - 47nf 100pf - 15nf 100pf - 4.7nf 0805* 100pf - 2.2? 100pf - 0.47? 100pf - 0.22? 100pf - 0.1? 100pf - 22nf 1206* 1.5? - 4.7? 1nf - 1? 1nf - 1.0? 1nf - 0.22? 1nf - 0.1? 1210* ? 1nf - 1.8? 1nf - 1? 1nf - 0.22? 1nf - 0.1? 1505 ??? 1nf - 0.1? 1nf - 27nf 1808 ?? 10nf - 0.33? 10nf - 0.33? 10nf - 0.1? 1812* ??? 10nf - 1? 10nf - 0.47? 1825* ??? 10nf - 1? 10nf - 0.47? 2220 ??? 10nf - 1.5? 10nf - 1.2? 2225 ??? 10nf - 2.2? 10nf - 1.5?
10 x7r dielectric capacitance range *reflow soldering only. notes: for higher voltage chips, see pages 20 and 21. preferred sizes are shaded size 0402* 0504* 0603* 0805 1206 1505 standard reel all paper all embossed all paper paper/embossed paper/embossed all embossed packaging (l) length mm 1.00 .10 1.27 .25 1.60 .15 2.01 .20 3.20 .20 3.81 .25 (in.) (.040 .004) (.050 .010) (.063 .006) (.079 .008) (.126 .008) (.150 .010) (w) width mm .50 .10 1.02 .25 .81 .15 1.25 .20 1.60 .20 1.27 .25 (in.) (.020 .004) (.040 .010) (.032 .006) (.049 .008) (.063 .008) (.050 .010) (t) max. thickness mm .60 1.02 .90 1.30 1.50 1.27 (in.) (.024) (.040) (.035) (.051) (.059) (.050) (t) terminal mm .25 .15 .38 .13 .35 .15 .50 .25 .50 .25 .50 .25 (in.) (.010 .006) (.015 .005) (.014 .006) (.020 .010) (.020 .010) (.020 .010) wvdc 16 25 50 50 100 10 16 25 50 100 10 16 25 50 100 10 16 25 50 100 50 100 cap 100 (pf) 120 150 180 220 270 330 390 470 560 680 820 1000 1200 1500 1800 2200 2700 3300 3900 4700 5600 6800 8200 cap. .010 (?) .012 .015 .018 .022 .027 .033 .039 .047 .056 .068 .082 .10 .12 .15 .18 .22 .27 .33 .47 .56 .68 .82 1.0 1.2 1.5 1.8 2.2 4.7 = paper tape = embossed tape l . . . . w . . . . t t
11 x7r dielectric capacitance range *reflow soldering only. notes: for higher voltage chips, see pages 20 and 21. preferred sizes are shaded size 1210 1808* 1812* 1825* 2220* 2225* standard reel packaging paper/embossed all embossed all embossed all embossed all embossed all embossed (l) length mm 3.20 .20 4.57 .25 4.50 .30 4.50 .30 5.7 0.4 5.72 .25 (in.) (.126 .008) (.180 .010) (.177 .012) (.177 .012) (.225 .016) (.225 .010) (w) width mm 2.50 .20 2.03 .25 3.20 .20 6.40 .40 5.0 0.4 6.35 .25 (in.) (.098 .008) (.080 .010) (.126 .008) (.252 .016) (.197 .016) (.250 .010) (t) max. thickness mm 1.70 1.52 1.70 1.70 2.30 1.70 (in.) (.067) (.060) (.067) (.067) (.090) (.067) (t) terminal mm .50 .25 .64 .39 .61 .36 .61 .36 .64 .39 .64 .39 (in.) (.020 .010) (.025 .015) (.024 .014) (.024 .014) (.025 .015) (.025 .015) wvdc 16 25 50 100 25 50 100 50 100 50 100 50 100 200 50 100 cap 1000 (pf) 1200 1500 1800 2200 2700 3300 3900 4700 5600 6800 8200 cap. .010 (?) .012 .015 .018 .022 .027 .033 .039 .047 .056 .068 .082 .10 .12 .15 .18 .22 .27 .33 .39 .47 .56 .68 .82 1.0 1.2 1.5 1.8 2.2 = paper tape = embossed tape l . . . . w . . . . t t
2 i. capacitance (farads) english: c = .224 k a t d metric: c = .0884 k a t d ii. energy stored in capacitors (joules, watt - sec) e = 1 2 cv 2 iii. linear charge of a capacitor (amperes) i = c dv dt iv. total impedance of a capacitor (ohms) z = r 2 s + (x c - x l ) 2 v. capacitive reactance (ohms) x c = 1 2 fc vi. inductive reactance (ohms) x l = 2 fl vii. phase angles: ideal capacitors: current leads voltage 90 ideal inductors: current lags voltage 90 ideal resistors: current in phase with voltage viii. dissipation factor (%) d.f.= tan d (loss angle) = e.s.r. = (2 fc) (e.s.r.) x c ix. power factor (%) p.f. = sine d (loss angle) = cos f (phase angle) p.f. = (when less than 10%) = df x. quality factor (dimensionless) q = cotan d (loss angle) = 1 d.f. xi. equivalent series resistance (ohms) e.s.r. = (d.f.) (xc) = (d.f.) / (2 fc) xii. power loss (watts) power loss = (2 fcv 2 ) (d.f.) xiii. kva (kilowatts) kva = 2 fcv 2 x 10 -3 xiv. temperature characteristic (ppm/?) t.c. = ct ?c 25 x 10 6 c 25 (t t ?25) xv. cap drift (%) c.d. = c 1 ?c 2 x 100 c 1 xvi. reliability of ceramic capacitors l 0 = v t xt t y l t ( v o )( t o ) xvii. capacitors in series (current the same) any number: 1 = 1 + 1 --- 1 c t c 1 c 2 c n c 1 c 2 two: c t = c 1 + c 2 xviii. capacitors in parallel (voltage the same) c t = c 1 + c 2 --- + c n xix. aging rate a.r. = % d c/decade of time xx. decibels db = 20 log v 1 v 2 ? pico x 10 -12 nano x 10 -9 micro x 10 -6 milli x 10 -3 deci x 10 -1 deca x 10 +1 kilo x 10 +3 mega x 10 +6 giga x 10 +9 tera x 10 +12 k = dielectric constant f = frequency l t = test life a = area l = inductance v t = test voltage t d = dielectric thickness d = loss angle v o = operating voltage v = voltage f = phase angle t t = test temperature t = time x & y = exponent effect of voltage and temp. t o = operating temperature r s = series resistance l o = operating life metric prefixes symbols basic capacitor formulas
3 how to order part number explanation example: 08055a101jat2a 0805 size (l" x w") 0402 0504 0603 0805 1005 0907 1206 1210 1505 1805 1808 1812 1825 2225 3640 5 voltage 10v = z 16v = y 25v = 3 50v = 5 100v = 1 200v = 2 250v = v 500v = 7 600v = c 1000v = a 1500v = s 2000v = g 2500v = w 3000v = h 4000v = j 5000v = k a dielectric c0g (np0) = a x7r = c x5r = d z5u = e y5v = g 101 capacitance code (2 significant digits + no. of zeros) examples: j capacitance tolerance a failure rate a = not applicable t terminations 2a special** code 10 pf = 100 100 pf = 101 1,000 pf = 102 22,000 pf = 223 220,000 pf = 224 1 ? = 105 c = ?25 pf* d = ?50 pf* f = ?% ( 3 25 pf) g = ?% ( 3 13 pf) j = ?% k = ?0% m = ?0% z = +80%, -20% p = +100%, -0% others: 7 = bulk cassette 9 = bulk * c&d tolerances for # 10 pf values. ** standard tape and reel material depends upon chip size and thickness. see individual part tables for tape material type for each capacitance value. note: unmarked product is standard. marked product is available on special request, please contact avx. standard packaging is shown in the individual tables. non-standard packaging is available on special request, please contact avx. standard: t = ni and tin plated a = standard product non-standard p = embossed unmarked m = embossed marked e = standard packaging marked low profile chips only max. thickness t = .66mm (.026") s = .56mm (.022") r = .46mm (.018") for values below 10 pf, use ??in place of decimal point, e.g., 9.1 pfd = 9r1. recommended: 2 =7" reel 4 =13" reel others: 7 = plated ni gold plated 1 = pd/ag packaging**
22 specification appearance no visual defects capacitance variation c0g (np0): 2.5% or .25pf, whichever is greater x7r: 7.5% z5u: 20% y5v: 20% q, tan delta to meet initial requirement insulation resistance c0g (np0), x7r: to meet initial requirement z5u, y5v: 3 initial value x 0.1 dielectric strength no problem observed measuring conditions step temperature ? time (minutes) 1 +65 +5/-0 15 2 pure water 2 0 3 15 2 nacl solution repeat cycle 2 times and wash with water and dry. store at room temperature for 48 4 hours (24 hours for c0g (np0)) and measure. general specifications environmental specification appearance no visual defects capacitance variation c0g (np0): 2.5% or .25pf, whichever is greater x7r: 7.5% z5u: 20% y5v: 20% q, tan delta to meet initial requirement insulation resistance c0g (np0), x7r: to meet initial requirement z5u, y5v: 3 initial value x 0.1 dielectric strength no problem observed measuring conditions step temperature ? time (minutes) c0g (np0), x7r: -55 2 1 z5u: +10 2 30 3 y5v: -30 2 2 room temperature # 3 3 c0g (np0), x7r: +125 2 30 3 z5u, y5v: +85 2 4 room temperature # 3 repeat for 5 cycles and measure after 48 hours 4 hours (24 hours for c0g (np0)) at room temperature. thermal shock immersion moisture resistance specification appearance no visual defects capacitance variation c0g (np0): 5% or .5pf, whichever is greater x7r: 10% z5u: 30% y5v: 30% q, tan delta c0g (np0): 3 30pf ........................q 3 350 3 10pf, < 30pf ...........q 3 275+5c/2 < 10pf ........................q 3 200+10c x7r: initial requirement + .5% z5u: initial requirement + 1% y5v: initial requirement + 2% insulation resistance 3 initial value x 0.3 measuring conditions step temp. ? humidity % time (hrs) 1 +25->+65 90-98 2.5 2 +65 90-98 3.0 3 +65->+25 80-98 2.5 4 +25->+65 90-98 2.5 5 +65 90-98 3.0 6 +65->+25 80-98 2.5 7 +25 90-98 2.0 7a -10 uncontrolled 7b +25 90-98 repeat 20 cycles (1-7) and store for 48 hours (24 hours for c0g (np0)) at room temperature before measuring. steps 7a & 7b are done on any 5 out of first 9 cycles.
23 general specifications environmental specification appearance no visual defects capacitance variation c0g (np0): 5% or .5pf, whichever is greater x7r: 10% z5u: 30% y5v: 30% q, tan delta c0g (np0): 3 30pf......................q 3 350 3 10pf, < 30pf.........q 3 275+5c/2 < 10pf ....................q 3 200+10c x7r: initial requirement + .5% z5u: initial requirement + 1% y5v: initial requirement + 2% insulation resistance 3 initial value x 0.3 measuring conditions store at 85 5% relative humidity and 85? for 1000 hours, without voltage. remove from test chamber and stabilize at room temperature and humidity for 48 4 hours (24 ? hours for c0g (np0)) before measuring. charge and discharge currents must be less than 50ma. steady state humidity (no load) specification appearance no visual defects capacitance variation c0g (np0): 5% or .5pf, whichever is greater x7r: 10% z5u: 30% y5v: 30% q, tan delta c0g (np0): 3 30pf .....................q 3 350 3 10pf,< 30pf .........q 3 275+5c/2 < 10pf ....................q 3 200+10c x7r: initial requirement + .5% z5u: initial requirement + 1% y5v: initial requirement + 2% load humidity specification appearance no visual defects capacitance variation c0g (np0): 3% or .3pf, whichever is greater x7r: 10% z5u: 30% y5v: 30% q, tan delta c0g (np0): 3 30pf......................q 3 350 3 10pf, < 30pf.........q 3 275+5c/2 < 10pf ....................q 3 200+10c x7r: initial requirement + .5% z5u: initial requirement + 1% y5v: initial requirement + 2% insulation resistance c0g (np0), x7r: to meet initial value x 0.3 z5u, y5v: 3 initial value x 0.1 charge devices with twice rated voltage in test chamber set at +125? 2? for c0g (np0) and x7r, +85 2? for z5u, and y5v for 1000 (+48,-0) hours. remove from test chamber and stabilize at room temperature for 48 4 hours (24 ? hours for c0g (np0)) before measuring. charge and discharge currents must be less than 50ma. load life insulation resistance c0g (np0), x7r: to meet initial value x 0.3 z5u, y5v: 3 initial value x 0.1 charge devices with rated voltage in test chamber set at 85 5% relative humidity and 85? for 1000 (+48,-0) hours. remove from test chamber and stabilize at room temperature and humidity for 48 4 hours (24 ? hours for c0g (np0)) before measuring. charge and discharge currents must be less than 50ma.
24 general specifications mechanical specification no evidence of peeling of end terminal measuring conditions after soldering devices to circuit board apply 5n (0.51kg f) for 10 1 seconds, please refer to figure 1. specification appearance: no visual defects capacitance within specified tolerance q, tan delta to meet initial requirement insulation resistance c0g (np0), x7r $ initial value x 0.3 z5u, y5v $ initial value x 0.1 measuring conditions vibration frequency 10-2000 hz maximum acceleration 20g swing width 1.5mm test time x, y, z axis for 2 hours each, total 6 hours of test end termination adherence resistance to vibration specification $ 95% of each termination end should be covered with fresh solder measuring conditions dip device in eutectic solder at 230 5? for 2 .5 seconds figure 2. bend strength figure 1. terminal adhesion solderability specification appearance: no visual defects capacitance variation c0g (np0): 5% or .5pf, whichever is larger x7r: 12% z5u: 30% y5v: 30% insulation resistance c0g (np0): 3 initial value x 0.3 x7r: 3 initial value x 0.3 z5u: 3 initial value x 0.1 y5v: 3 initial value x 0.1 measuring conditions please refer to figure 2 deflection: 2mm test time: 30 seconds bend strength specification appearance: no serious defects, <25% leaching of either end terminal capacitance variation c0g (np0): 2.5% or 2.5pf, whichever is greater x7r: 7.5% z5u: 20% y5v: 20% q, tan delta to meet initial requirement insulation resistance to meet initial requirement dielectric strength no problem observed measuring conditions dip device in eutectic solder at 260?, for 1 minute. store at room temperature for 48 hours (24 hours for c0g (np0)) before measuring electrical parameters. part sizes larger than 3.20mm x 2.49mm are reheated at 150? for 30 ? seconds before performing test. resistance to solder heat speed = 1mm/sec r340mm supports 2mm deflection 45mm 45mm 5n force device under test test board
31 0805 size (l" x w") 5 voltage 50v = 5 100v = 1 200v = 2 c dielectric 1b cg = a 2r1 = c 2f4 = g 103 capacitance code m capacitance tolerance see dielectrics c0g, x7r, y5v t specification cecc32101-801 t terminations t = plated ni and sn 2 marking packaging 2 = 7" reel 4 = 13" reel a special code a = std. product part number (example) range of approved components case dielectric voltage and capacitance range size type 50v 100v 200v 1bcg 0603 1b cg 0.47pf - 150pf 0.47pf - 120pf 0.47pf - 100pf 0805 1b cg 0.47pf - 560pf 0.47pf - 560pf 0.47pf - 330pf 1206 1b cg 0.47pf - 3.3nf 0.47pf - 3.3nf 0.47pf - 1.5nf 1210 1b cg 0.47pf - 4.7nf 0.47pf - 4.7nf 0.47pf - 2.7nf 1808 1b cg 0.47pf - 6.8nf 0.47pf - 6.8nf 0.47pf - 4.7nf 1812 1b cg 0.47pf - 15nf 0.47pf - 15nf 0.47pf - 10nf 2220 1b cg 0.47pf - 39nf 0.47pf - 39nf 0.47pf - 15nf 2r1 0603 2r1 10pf - 6.8nf 10pf - 6.8nf 10pf - 1.2nf 0805 2r1 10pf - 33nf 10pf - 18nf 10pf - 3.3nf 1206 2r1 10pf - 100nf 10pf - 68nf 10pf - 18nf 1210 2r1 10pf - 150nf 10pf - 100nf 10pf - 27nf 1808 2r1 10pf - 270nf 10pf - 180nf 10pf - 47nf 1812 2r1 10pf - 470nf 10pf - 330nf 10pf - 100nf 2220 2r1 10pf - 1.2? 10pf - 680nf 10pf - 220nf 2f4 0805 2f4 10pf - 100nf 1206 2f4 10pf - 330nf 1210 2f4 10pf - 470nf 1808 2f4 10pf - 560nf 1812 2f4 10pf - 1.8? 2220 2f4 10pf - 2.2? european detail specifications cecc 32 101-801/chips standard european ceramic chip capacitors
32 packaging of chip components automatic insertion packaging tape & reel quantities all tape and reel specifications are in compliance with rs481. 8mm 12mm paper or embossed carrier 0805, 1005, 1206, 1210 embossed only 0504, 0907 1505, 1805, 1812, 1825 1808 2220, 2225 paper only 0402, 0603 qty. per reel/7" reel 2,000 or 4,000 (1) 3,000 1,000 qty. per reel/13" reel 10,000 10,000 4,000 (1) dependent on chip thickness. low profile chips shown on page 27 are 5,000 per reel for 7" reel. 0402 size chips are 10,000 per 7" reels and are not available on 13" reels. for 3640 size chip contact factory for quantity per reel. reel dimensions tape a b* c d* n w 1 w 2 w 3 size (1) max. min. min. min. max. +1.0 7.9 min. 8mm 8.4 ?.0 14.4 (.311) (.331 +.060 ) (.567) 10.9 max. 330 1.5 13.0?.20 20.2 50 ?.0 (.429) (12.992) (.059) (.512?008) (.795) (1.969) +2.0 11.9 min. 12mm 12.4 ?.0 18.4 (.469) (.488 +.076 ) (.724) 15.4 max. ?.0 (.607) metric dimensions will govern. english measurements rounded and for reference only. (1) for tape sizes 16mm and 24mm (used with chip size 3640) consult eia rs-481 latest revision.
33 tape size b 1 d 1 fp 1 rt 2 wa 0 b 0 k 0 max. min. min. see note 6 see note 5 see note 2 8mm 4.55 1.0 3.5 0.05 4.0 0.10 25 2.5 max see note 1 (.179) (.039) (.138 .002) (.157 .004) (.984) (.098) 12mm 8.2 1.5 5.5 0.05 4.0 0.10 30 6.5 max. 12.0 .30 see note 1 (.323) (.059) (.217 .002) (.157 .004) (1.181) (.256) (.472 .012) 8mm 4.55 1.0 3.5 0.05 2.0 0.10 25 2.5 max. see note 1 1/2 pitch (.179) (.039) (.138 .002) 0.79 .004 (.984) (.098) 12mm 8.2 1.5 5.5 0.05 8.0 0.10 30 6.5 max. 12.0 .30 see note 1 double (.323) (.059) (.217 .002) (.315 .004) (1.181) (.256) (.472 .012) pitch embossed carrier configuration 8 & 12mm tape only 8 & 12mm embossed tape metric dimensions will govern constant dimensions tape size d 0 ep 0 p 2 t max. t 1 g 1 g 2 8mm 8.4 +0.10 1.75 0.10 4.0 0.10 2.0 0.05 0.600 0.10 0.75 0.75 -0.0 and (.059 +.004 ) (.069 .004) (.157 .004) (.079 .002) (.024) (.004) (.030) (.030) 12mm -0.0 max. min. min. see note 3 see note 4 variable dimensions notes: 1. a 0 , b 0 , and k 0 are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. the clearance between the end of the terminals or body of the component to the sides and depth of the cavity (a 0 , b 0 , and k 0 ) must be within 0.05 mm (.002) min. and 0.50 mm (.020) max. the clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (se e sketches c & d). 2. tape with components shall pass around radius ??without damage. the minimum trailer length (note 2 fig. 3) may require add itional length to provide r min. for 12 mm embossed tape for reels with hub diameters approaching n min. (table 4). 3. g 1 dimension is the flat area from the edge of the sprocket hole to either the outward deformation of the carrier tape between the embossed cavities or to the edge of the cavity whichever is less. 4. g 2 dimension is the flat area from the edge of the carrier tape opposite the sprocket holes to either the outward deformation of t he carrier tape between the embossed cavity or to the edge of the cavity whichever is less. 5. the embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. dimensions of embossment location and hole location shall be applied independent of each other. 6. b 1 dimension is a reference dimension for tape feeder clearance only. 8.0 +0.3 -0.1 (.315 +.012 ) -.004 8.0 +0.3 -0.1 (.315 +.012 ) -.004
tape size p 1 fwa 0 b 0 t 8mm 4.0 0.10 3.5 0.05 see note 1 see note 3 (.157 .004) (.138 .002) 12mm 4.0 .010 5.5 0.05 12.0 0.3 (.157 .004) (.217 .002) (.472 .012) 8mm 2.0 0.10 3.5 0.05 1/2 pitch (.079 .004) (.138 .002) 12mm 8.0 0.10 5.5 0.05 12.0 0.3 double (.315 .004) (.217 .002) (.472 .012) pitch 34 paper carrier configuration 8 & 12mm tape only 8 & 12mm paper tape metric dimensions will govern constant dimensions tape size d 0 ep 0 p 2 t 1 g 1 g 2 r min. 8mm 1.5 +0.1 1.75 0.10 4.0 0.10 2.0 0.05 0.10 0.75 0.75 25 (.984) -0.0 and (.059 +.004 ) (.069 .004) (.157 .004) (.079 .002) (.004) (.030) (.030) see note 2 12mm -.000 max. min. min. variable dimensions notes: 1. a 0 , b 0 , and t are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body di mensions of the component. the clearance between the ends of the terminals or body of the component to the sides and depth of the cavity (a 0 , b 0 , and t) must be within 0.05 mm (.002) min. and 0.50 mm (.020) max. the clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (se e sketches a & b). 2. tape with components shall pass around radius ??without damage. 3. 1.1 mm (.043) base tape and 1.6 mm (.063) max. for non-paper base compositions. 8.0 +0.3 -0.1 (.315 +.012 ) -.004 8.0 +0.3 -0.1 (.315 +.012 ) -.004 bar code labeling standard avx bar code labeling is available and follows latest version of eia-556-a.
35 bulk case packaging case quantities part size 0402 0603 0805 qty. 10,000 (t=0.6mm) (pcs / cassette) 80,000 15,000 5,000 (t? 3 0.6mm) benefits bulk feeder ?easier handling ?smaller packaging volume (1/20 of t/r packaging) ?easier inventory control ?flexibility ?recyclable case dimensions shutter slider attachment base 110mm 12mm 36mm case cassette gate shooter chips expanded drawing mounter head
36 general description formulations ? multilayer ceramic capacitors are available in both class 1 and class 2 formulations. temperature compensating formulation are class 1 and temperature stable and general application formulations are classified as class 2. class 1 ? class 1 capacitors or temperature compensating capacitors are usually made from mixtures of titanates where barium titanate is normally not a major part of the mix. they have predictable temperature coefficients and in general, do not have an aging characteristic. thus they are the most stable capacitor available. the most popular class 1 multilayer ceramic capacitors are c0g (np0) temperature compensating capacitors (negative-positive 0 ppm/?). class 2 eia class 2 capacitors typically are based on the chemistry of barium titanate and provide a wide range of capacitance values and temperature stability. the most commonly used class 2 dielectrics are x7r and y5v. the x7r provides intermediate capacitance values which vary only ?5% over the temperature range of -55? to 125?. it finds applications where stability over a wide temperature range is required. the y5v provides the highest capacitance values and is used in applications where limited temperature changes are expected. the capacitance value for y5v can vary from 22% to -82% over the -30? to 85? temperature range. the z5u dielectric is between x7r and y5v in both stability and capacitance range. all class 2 capacitors vary in capacitance value under the influence of temperature, operating voltage (both ac and dc), and frequency. for additional information on perfor- mance changes with operating conditions, consult avx? software, spicap. basic construction ? a multilayer ceramic (mlc) capaci- tor is a monolithic block of ceramic containing two sets of offset, interleaved planar electrodes that extend to two opposite surfaces of the ceramic dielectric. this simple structure requires a considerable amount of sophistication, both in material and manufacture, to produce it in the quality and quantities needed in today? electronic equipment. ceramic layer electrode terminated edge terminated edge end terminations margin electrodes
37 general description effects of voltage ? variations in voltage have little effect on class 1 dielectric but does affect the capacitance and dissipation factor of class 2 dielectrics. the application of dc voltage reduces both the capacitance and dissipation factor while the application of an ac voltage within a reasonable range tends to increase both capacitance and dissipation factor readings. if a high enough ac voltage is applied, eventually it will reduce capacitance just as a dc voltage will. figure 2 shows the effects of ac voltage. capacitor specifications specify the ac voltage at which to measure (normally 0.5 or 1 vac) and application of the wrong voltage can cause spurious readings. figure 3 gives the voltage coefficient of dissipation factor for various ac voltages at 1 kilohertz. applications of different frequencies will affect the percentage changes versus voltages. the effect of the application of dc voltage is shown in figure 4. the voltage coefficient is more pronounced for higher k dielectrics. these figures are shown for room tem- perature conditions. the combination characteristic known as voltage temperature limits which shows the effects of rated voltage over the operating temperature range is shown in figure 5 for the military bx characteristic. cap. change vs. d.c. volts avx x7r t.c. typical cap. change vs. temperature avx x7r t.c. effects of time ? class 2 ceramic capacitors change capacitance and dissipation factor with time as well as tem- perature, voltage and frequency. this change with time is known as aging. aging is caused by a gradual re-alignment of the crystalline structure of the ceramic and produces an exponential loss in capacitance and decrease in dissipation factor versus time. a typical curve of aging rate for semi- stable ceramics is shown in figure 6. if a class 2 ceramic capacitor that has been sitting on the shelf for a period of time, is heated above its curie point, (125? for 4 hours or 150? for 1 2 hour will suffice) the part will de-age and return to its initial capacitance and dissi- pation factor readings. because the capacitance changes rapidly, immediately after de-aging, the basic capacitance measurements are normally referred to a time period some- time after the de-aging process. various manufacturers use different time bases but the most popular one is one day or twenty-four hours after ?ast heat.?change in the aging curve can be caused by the application of voltage and other stresses. the possible changes in capacitance due to de-aging by heating the unit explain why capacitance changes are allowed after test, such as temperature cycling, moisture resistance, etc., in mil specs. the application of high voltages such as dielectric withstanding voltages also 25% 50% 75% 100% percent rated volts capacitance change percent 2.5 0 -2.5 -5 -7.5 -10 0vdc rvdc -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 temperature degrees centigrade capacitance change percent +20 +10 0 -10 -20 -30 figure 2 50 40 30 20 10 0 12.5 25 37.5 50 volts ac at 1.0 khz capacitance change percent cap. change vs. a.c. volts avx x7r t.c. figure 3 curve 3 - 25 vdc rated capacitor curve 2 - 50 vdc rated capacitor curve 1 - 100 vdc rated capacitor curve 3 curve 2 curve 1 .5 1.0 1.5 2.0 2.5 ac measurement volts at 1.0 khz dissipation factor percent 10.0 8.0 6.0 4.0 2.0 0 d.f. vs. a.c. measurement volts avx x7r t.c. figure 4 figure 5
tends to de-age capacitors and is why re-reading of capac- itance after 12 or 24 hours is allowed in military specifica- tions after dielectric strength tests have been performed. effects of frequency ? frequency affects capacitance and impedance characteristics of capacitors. this effect is much more pronounced in high dielectric constant ceramic formulation that is low k formulations. avx? spicap soft- ware generates impedance, esr, series inductance, series resonant frequency and capacitance all as functions of fre- quency, temperature and dc bias for standard chip sizes and styles. it is available free from avx. effects of mechanical stress ? high ??dielectric ceramic capacitors exhibit some low level piezoelectric reactions under mechanical stress. as a general statement, the piezoelectric output is higher, the higher the dielectric constant of the ceramic. it is desirable to investigate this effect before using high ??dielectrics as coupling capaci- tors in extremely low level applications. reliability ? historically ceramic capacitors have been one of the most reliable types of capacitors in use today. the approximate formula for the reliability of a ceramic capacitor is: l o = v t x t t y l t v o t o where l o = operating life t t = test temperature and l t = test life t o = operating temperature v t = test voltage in ? v o = operating voltage x,y = see text historically for ceramic capacitors exponent x has been considered as 3. the exponent y for temperature effects typically tends to run about 8. a capacitor is a component which is capable of storing electrical energy. it consists of two conductive plates (elec- trodes) separated by insulating material which is called the dielectric. a typical formula for determining capacitance is: c = .224 ka t c = capacitance (picofarads) k = dielectric constant (vacuum = 1) a = area in square inches t = separation between the plates in inches (thickness of dielectric) .224 = conversion constant (.0884 for metric system in cm) capacitance ? the standard unit of capacitance is the farad. a capacitor has a capacitance of 1 farad when 1 coulomb charges it to 1 volt. one farad is a very large unit and most capacitors have values in the micro (10 -6 ), nano (10 -9 ) or pico (10 -12 ) farad level. dielectric constant in the formula for capacitance given above the dielectric constant of a vacuum is arbitrarily cho- sen as the number 1. dielectric constants of other materials are then compared to the dielectric constant of a vacuum. dielectric thickness ? capacitance is indirectly propor- tional to the separation between electrodes. lower voltage requirements mean thinner dielectrics and greater capaci- tance per volume. area ? capacitance is directly proportional to the area of the electrodes. since the other variables in the equation are usually set by the performance desired, area is the easiest parameter to modify to obtain a specific capacitance within a material group. 38 1 10 100 1000 10,000 100,000 hours capacitance change percent +1.5 0 -1.5 -3.0 -4.5 -6.0 -7.5 characteristic max. aging rate %/decade c0g (np0) x7r z5u y5v none 2 3 5 figure 6 typical curve of aging rate x7r dielectric s s s s general description
39 general description energy stored ? the energy which can be stored in a capacitor is given by the formula: e = 1 2 cv 2 e = energy in joules (watts-sec) v = applied voltage c = capacitance in farads potential change ? a capacitor is a reactive component which reacts against a change in potential across it. this is shown by the equation for the linear charge of a capacitor: i ideal = c dv dt where i = current c = capacitance dv/dt = slope of voltage transition across capacitor thus an infinite current would be required to instantly change the potential across a capacitor. the amount of current a capacitor can ?ink?is determined by the above equation. equivalent circuit a capacitor, as a practical device, exhibits not only capacitance but also resistance and induc- tance. a simplified schematic for the equivalent circuit is: c = capacitance l = inductance r s = series resistance r p = parallel resistance reactance ? since the insulation resistance (r p ) is normally very high, the total impedance of a capacitor is: z = r 2 s + (x c - x l ) 2 where z = total impedance r s = series resistance x c = capacitive reactance = 1 2 fc x l = inductive reactance = 2 fl the variation of a capacitor? impedance with frequency determines its effectiveness in many applications. phase angle ? power factor and dissipation factor are often confused since they are both measures of the loss in a capacitor under ac application and are often almost identi- cal in value. in a ?erfect?capacitor the current in the capacitor will lead the voltage by 90? in practice the current leads the voltage by some other phase angle due to the series resistance r s . the comple- ment of this angle is called the loss angle and: power factor (p.f.) = cos f or sine d dissipation factor (d.f.) = tan d for small values of d the tan and sine are essentially equal which has led to the common interchangeability of the two terms in the industry. equivalent series resistance ? the term e.s.r. or equivalent series resistance combines all losses both series and parallel in a capacitor at a given frequency so that the equivalent circuit is reduced to a simple r-c series connection. dissipation factor ? the df/pf of a capacitor tells what percent of the apparent power input will turn to heat in the capacitor. dissipation factor = e.s.r. = (2 fc) (e.s.r.) x c the watts loss are: watts loss = (2 fcv 2 ) (d.f.) very low values of dissipation factor are expressed as their reciprocal for convenience. these are called the ??or quality factor of capacitors. parasitic inductance the parasitic inductance of capac- itors is becoming more and more important in the decou- pling of today? high speed digital systems. the relationship between the inductance and the ripple voltage induced on the dc voltage line can be seen from the simple inductance equation: v = l di dt r l r c p s ? d i (ideal) i (actual) phase angle loss angle v ir s f e.s.r. c
40 the seen in current microprocessors can be as high as 0.3 a/ns, and up to 10a/ns. at 0.3 a/ns, 100ph of parasitic inductance can cause a voltage spike of 30mv. while this does not sound very drastic, with the vcc for microproces- sors decreasing at the current rate, this can be a fairly large percentage. another important, often overlooked, reason for knowing the parasitic inductance is the calculation of the resonant frequency. this can be important for high frequency, by- pass capacitors, as the resonant point will give the most signal attenuation. the resonant frequency is calculated from the simple equation: f res = 1 2 p lc insulation resistance ? insulation resistance is the resis- tance measured across the terminals of a capacitor and consists principally of the parallel resistance r p shown in the equivalent circuit. as capacitance values and hence the area of dielectric increases, the i.r. decreases and hence the product (c x ir or rc) is often specified in ohm farads or more commonly megohm-microfarads. leakage current is determined by dividing the rated voltage by ir (ohm? law). dielectric strength ? dielectric strength is an expression of the ability of a material to withstand an electrical stress. although dielectric strength is ordinarily expressed in volts, it is actually dependent on the thickness of the dielectric and thus is also more generically a function of volts/mil. dielectric absorption ? a capacitor does not discharge instantaneously upon application of a short circuit, but drains gradually after the capacitance proper has been dis- charged. it is common practice to measure the dielectric absorption by determining the ?eappearing voltage?which appears across a capacitor at some point in time after it has been fully discharged under short circuit conditions. corona ? corona is the ionization of air or other vapors which causes them to conduct current. it is especially prevalent in high voltage units but can occur with low volt ages as well where high voltage gradients occur. the energy discharged degrades the performance of the capacitor and can in time cause catastrophic failures. di dt general description ?
41 surface mounting guide mlc chip capacitors component pad design component pads should be designed to achieve good sol- der filets and minimize component movement during reflow soldering. pad designs are given below for the most com- mon sizes of multilayer ceramic capacitors for both wave and reflow soldering. the basis of these designs is: ?pad width equal to component width. it is permissible to decrease this to as low as 85% of component width but it is not advisable to go below this. ?pad overlap 0.5mm beneath component. ?pad extension 0.5mm beyond components for reflow and 1.0mm for wave soldering. d1 d2 d3 d4 d5 case size d1 d2 d3 d4 d5 0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02) 0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03) 0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05) 1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06) 1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10) 1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08) 1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12) 1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25) 2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20) 2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25) dimensions in millimeters (inches) reflow soldering
42 wave soldering component spacing for wave soldering components, must be spaced sufficiently far apart to avoid bridging or shadowing (inability of solder to penetrate properly into small spaces). this is less impor- tant for reflow soldering but sufficient space must be allowed to enable rework should it be required. preheat & soldering the rate of preheat should not exceed 4?/second to prevent thermal shock. a better maximum figure is about 2?/second. for capacitors size 1206 and below, with a maximum thickness of 1.25mm, it is generally permissible to allow a temperature differential from preheat to soldering of 150?. in all other cases this differential should not exceed 100?. for further specific application or process advice, please consult avx. cleaning care should be taken to ensure that the capacitors are thoroughly cleaned of flux residues especially the space beneath the capacitor. such residues may otherwise become conductive and effectively offer a low resistance bypass to the capacitor. ultrasonic cleaning is permissible, the recommended conditions being 8 watts/litre at 20-45 khz, with a process cycle of 2 minutes vapor rinse, 2 minutes immersion in the ultrasonic solvent bath and finally 2 minutes vapor rinse. surface mounting guide mlc chip capacitors d1 d2 d3 d4 d5 case size d1 d2 d3 d4 d5 0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03) 0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05) 1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06) 1210 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 2.50 (0.10) dimensions in millimeters (inches) 3 1mm (0.04) 3 1.5mm (0.06) 3 1mm (0.04)
43 surface mounting guide mlc chip capacitors application notes storage good solderability is maintained for at least twelve months, provided the components are stored in their ?s received packaging at less than 40? and 70% rh. solderability terminations to be well soldered after immersion in a 60/40 tin/lead solder bath at 235 ?? for 2? seconds. leaching terminations will resist leaching for at least the immersion times and conditions shown below. recommended soldering profiles general surface mounting chip multilayer ceramic capacitors are designed for soldering to printed circuit boards or other substrates. the construction of the components is such that they will withstand the time/temperature profiles used in both wave and reflow soldering methods. handling chip multilayer ceramic capacitors should be handled with care to avoid damage or contamination from perspiration and skin oils. the use of tweezers or vacuum pick ups is strongly recommended for individual components. bulk handling should ensure that abrasion and mechanical shock are minimized. taped and reeled components provides the ideal medium for direct presentation to the placement machine. any mechanical shock should be minimized during handling chip multilayer ceramic capacitors. preheat it is important to avoid the possibility of thermal shock during soldering and carefully controlled preheat is therefore required. the rate of preheat should not exceed 4?/second and a target figure 2?/second is recommended. although an 80? to 120? temperature differential is preferred, recent developments allow a temperature differential between the component surface and the soldering temper- ature of 150? (maximum) for capacitors of 1210 size and below with a maximum thickness of 1.25mm. the user is cautioned that the risk of thermal shock increases as chip size or temperature differential increases. soldering mildly activated rosin fluxes are preferred. the minimum amount of solder to give a good joint should be used. excessive solder can lead to damage from the stresses caused by the difference in coefficients of expansion between solder, chip and substrate. avx terminations are suitable for all wave and reflow soldering systems. if hand soldering cannot be avoided, the preferred technique is the utilization of hot air soldering tools. cooling natural cooling in air is preferred, as this minimizes stresses within the soldered joint. when forced air cooling is used, cooling rate should not exceed 4?/second. quenching is not recommended but if used, maximum temperature differentials should be observed according to the preheat conditions above. cleaning flux residues may be hygroscopic or acidic and must be removed. avx mlc capacitors are acceptable for use with all of the solvents described in the specifications mil-std- 202 and eia-rs-198. alcohol based solvents are acceptable and properly controlled water cleaning systems are also acceptable. many other solvents have been proven successful, and most solvents that are acceptable to other components on circuit assemblies are equally acceptable for use with ceramic capacitors. termination type solder solder immersion time tin/lead/silver temp. ? seconds nickel barrier 60/40/0 260? 30? reflow 300 250 200 150 100 50 0 solder temp. 10 sec. max 1min 1min (minimize soldering time) natural cooling 220 c to 250 c preheat wave 300 250 200 150 100 50 0 solder temp. (preheat chips before soldering) t/maximum 150 c 3 sec. max 1 to 2 min preheat natural cooling 230 c to 250 c t

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